As dimensions of semiconductor devices shrink, isolation techniques have had to move from conventional local oxidation of silicon ("LOCOS") isolation techniques to shallow trench isolation ("STI").
In fabricating an STI structure, a trench is created in a substrate. The trench marks an end of the active area of the device to be fabricated. Under the current state of the art, the walls of the trench created are very close to being perpendicular with the surface of the substrate. The perpendicular nature of the walls leads to several problems in the fabrication of the remainder of the semiconductor device.
One problem occurs during the implantation of a connecting layer, for example a layer of N+ ions, into the substrate after the creation of the trench and the filling of the trench with field oxide. The connecting layer of N+ ions will connect metal later formed on the substrate outside of the trench which will make up the circuits of the connected devices. Because the walls of the trench are very close to perpendicular and the implant direction is also close to perpendicular, the N+ ions do not implant into the walls of the trench. Also, the depth of the close-to-perpendicular trench might not be optimized for the implant to reach the bottom of the trench. This creates gaps in the connecting layer which would cause an open circuit, preventing the connectivity of the circuits.
A second problem is associated with the active areas in the upper comers of the trench. After the trench is created, it is filled with field oxide. Then the wafer is planarized using chemical-mechanical polishing (CMP). A thin layer of tunnel oxide is grown on the substrate. However, due to the abrupt drop-off of the trench walls and subsequent processes, the field oxide around the edges of the gate and near the trench could become recessed. This could cause the tunnel oxide in this area to thin or become damaged. This creates a layer of tunnel oxide which is of uneven thickness, causing undesirable variances in the electric field generated throughout the tunnel oxide during programming and/or erasing operations. This compromises the reliability of the device.
The corners at the upper portion of the trench are known high stress points which, during an oxidation cycle, can inhibit the formation of a good quality oxide. The lack of a good quality gate oxide adversely affects device performance and reliability.
A third problem is the device's vulnerability to a misalignment of the mask used to form metal contacts, due to the perpendicular nature of the walls of the trench. The mask is created by etching a layer of interlayer dielectric which has been deposited on the p-type substrate and the trench area. In an aligned situation, the etch exposes portions of the substrate at which metal contacts will be formed, while protecting the trench area. No portion of the trench area is etched. But in a misaligned situation, the etch does occur at least at a portion of the trench area. Since the etch continues until substrate is reached, a portion of the field oxide inside the trench can be etched away along with the interlayer dielectric above it. This exposes a wall of the trench. When the metal contact material is laid to plug the holes in the mask, it will touch the wall of the trench. Since there are gaps in the connecting layer along the trench walls, as explained above, the metal contact material is directly touching the substrate, causing a short to substrate.
Accordingly, what is needed is a method for providing an STI structure profile which will prevent gaps in the connecting layer, prevent oxide film erosion during the various steps in the processing sequence to protect the stressed upper comers of the trench, and prevent a short to substrate in the event of a misalignment of the mask during metal contact formation.